WDCLK input vs. I2S frame output phase relationship

[bluecoast]

I want to clock the DICE via WDCLKIN at 1Fs, and also have it be an I2S master. I'm wondering if the I2S WDCLK will happen in sync with or a fixed time after the WDCLKIN I supply to the DICE PLL, or whether the phase relationship between them will be random.

Thanks.

[giana]

This is more about firmware issue, so I will forward this to more appropriate personal.

It is possible to sync DICE with 1Fs and worked as I2S master. However, only at start up time, DICE need to have 25MHz (or 24.576Mhz) range clock to be fed to XTAL1 input pin. With this condition, I2S WDCLK generated by DICE PLL can be sync with WDCLKIN.

[bluecoast]

Thanks Giana,

I think I may have answered my own question -- just had to experiment. FCK0 seems to always be 180 degrees out of phase with EXT_FBR -- at least with the EVM firmware.

Andrew

[giana]

Hi Andrew,

The I2S (or InS) format is as definition, frame sync signal FSK is start with "Low" for L-ch and then goes "High" for R-ch. On the other hand, Word sync signal is often generated as L-ch for "High" and R-ch for "Low". If this is the case they are completely in sync, but appeared as 180 degree out.